The present invention relates in general to semiconductor devices and their fabrication. More specifically, the present invention relates to improved fabrication methodologies and resulting structures for a vertical field effect transistor (VFET) having reduced gate-induced drain-leakage (GIDL) current.
In an integrated circuit (IC) having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. The term “planar” is often used to describe a conventional geometry for MOSFETs in which the various component parts of the MOSFET device are laid down as planes or layers.
VFETs are one example of a non-planar MOSFET geometry. VFETs employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density along with increased performance over planar or lateral devices. In VFETs, the source-to-drain current flows in a direction that is perpendicular to a major surface of the substrate. The fin forms a vertical channel region of the VFET. A source region and a drain region are in electrical contact with the top and bottom ends of the channel region, and a gate is located on sidewalls of the fins. An important performance parameter in designing VFETs is minimizing the presence of off-state leakage currents such as GIDL current.